Z01X™ is a high-speed functional fault simulator for Verilog
designs. Its high performance, memory efficient, C2™ algorithm
combined with its integrated expert test system, Fault Manager™,
makes fault simulation of large designs a reality.
Test ordering with redundant test elimination
Verilog IEEE 1364 (1995, 2001 & 2005)
Behavioral, RTL, UDP, gate and switch level
Full timing, path delays, negative timing checks, SDF
Stuck-bt, transition and Bridge fault models
Hyper fault checking
Automatic crash recovery
STIL, WGL, VCD/eVCD and testbench stimulus
Test Ordering and Redundant Test Elimination
Prior to fault simulation Z01X performs testability analysis of
the design and test suite to determine the quality of each test.
Tests are then ranked best-to-worst and fault simulation is begun
using the one with the highest Test Quality. After each test is
simulated, Testability Analysis is run again and the tests are
re-ranked. By running tests in the most effective order Z01X can
reduce fault simulation time as well as tester time. Z01X also
eliminates redundant tests, often 50% or more of the test suite.
A major feature of Z01X is its
ability to sort through tests to find near optimal tests. In
the diagram above, Z01X eliminated 11 out of the 21 tests
provided by the customer thereby significantly reducing
Z01X supports the full Verilog IEEE 1364-2001 language, including
behavioral, RTL, UDP, gate and switch-level. No re-modeling of
complex modules such as memories or PLL's is required.
The stuck-at fault is the most common fault model and it
represents several types of defects. Z01X can either generate a
list of stuck-at faults, including fault collapsing, or a fault
list can be imported from other tools such as FastScan™, TetraMAX®
A transition fault models a signal which is delayed by 1 or more
clock cycles. Z01X models slow-to-rise and slow-to-fall transition
faults. The transition fault list can either be generated by Z01X
or imported from other tools, such as FastScan or TetraMAX. The
detected faults from a stuck-at fault simulation can also be used
as a starting transition fault list. Multiple clock domains are
supported by performing one fault simulation for each clock
Bridge faults are used to model two signals that are physically
shorted. Z01X supports 4 bridge fault modes, wired-or, wired-and,
X dominate and Y dominate. Unlike stuck-at and transition faults,
which can be generated from a netlist, the bridge fault list must
be extracted from the physical layout.
Hyper Fault Checking
The concurrent algorithm is subject to faults which can use
excessive amount of simulation time or memory. These faults are
commonly referred to as hyper faults. Z01X has automatic and
user-defined checking for hyperactive and hypertrophic faults. A
hyperactive fault can cause excessively long simulation times. A
hypertrophic fault can cause excessive memory usage.
Fault simulation can be very CPU intensive. Distributing the fault
simulation across multiple CPU's will result in a near linear
reduction in wall clock time. Each CPU simulates the complete
design with a portion of the fault list. A fault simulation which
takes 12 hours on a single CPU would take approximately 3 hours
using 4 CPU's. Distributed fault simulation with Z01X can easily
be setup using named hosts or with Platform LSF® from Platform
Automatic Crash Recovery
Z01X automatically re-starts any partition which fails in a
distributed simulation with very little loss of data. Should the
master process fail the fault simulation can be re-started and
Z01X will automatically resume from the point of failure.
To accurately model the tester Z01X accepts STIL or WGL stimulus.
VCD/eVCD or a Verilog testbench can also be used. Parallel loading
can be done with STIL or WGL for verification of ATPG scan
vectors. Z01X automatically verifies correct simulation when using
STIL, WGL or VCD/eVCD stimulus.
Z01X supports many of the Verifault-XL system tasks, such as $fs_add()
and $fs_strobe(), as well as Verifault-XL compiler directives,
such as `enable_portfaults and `suppress_faults.